Evaluating NEX for RTL Design: A Purdue SoCET Case Study

Fri, 26 Jun 2026 00:21:10 +0200

Hardware designers evaluate AI differently than most software developers. Beyond code generation, they care about whether a system can understand architectural intent, navigate large RTL projects, respect design constraints, and accelerate verification workflows.

To evaluate these capabilities, ChipNexus partnered with Purdue University’s System-on-Chip Extension Technologies (SoCET) group to assess NEX across increasingly complex RTL design tasks, ranging from a 32-bit ALU to a dual-core cache-coherent RV32I processor. The evaluation involved multiple members of the SoCET program with varying levels of hardware design experience. The most complex design, estimated at roughly 100 hours of manual effort, was completed in approximately 2.5–3.5 hours using NEX.

Case Study on ChipNexus Blog | Agentic AI for Chip Design

Evaluating NEX for RTL Design: A Purdue SoCET Case Study